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| NTE2055 Integrated Circuit CMOS, 3 1/2 Digit A/D Converter Description: The NTE2055 is a high performance, low power, 3 1/2 digit A/D converter combining both linear CMOS and digital CMOS circuits on a single monolithic IC. Available in a 24-Lead DIP type package, this device is designed to minimize use of external components. With two external resistors and two external capacitors, the system forms a dual slope A/D converter with automatic zero correction and automatic polarity. The NTE2055 is ratiometric and may be used over a full-scale range from 1.999V to 199.9mV. Systems using this device may operate over a wide range of power supply voltages for ease of use with batteries, or with standard 5V supplies. The output drive conforms with standard B-Series CMOS specifications and can drive a low-power Schottky TTL load. The high impedance MOS inputs allow applications in current and resistance meters as well as voltmeters. In addition to DVM/DPM applications, the NTE2055 finds use in digital thermometers, digital scales, remote A/D, A/D control systems, and in MPU systems. Features: D Accuracy: 0.05% of Reading 1 Count D Two Voltage Ranges: 1.999V and 199.9mV D Up to 25 Conversions /s D Zin > 100M D Auto-Polarity and Auto-Zero D Single Positive Voltage Reference D Standard B-Series CMOS Outputs: Drives One Low Power Schottky Load D Uses On-Chip System Clock, or External Clock D Wide Supply Range: e.g., 4.5V to 8.0V D Overrange and Underrange Signals Available D Operates in Auto Ranging Circuits D Operates with LED and LCD Displays D Low External Component Count D Chip Complexity: 1326 FETs Absolute Maximum Ratings: DC Supply Voltage, VDD to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V Voltage, Ant Pin, Referenced to VEE, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V DC Input Current, Per Pin, Iin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VEE (Vin or Vout) VDD. Recommended Operating Conditions: (VSS = 0 or VEE) DC Supply Voltage VDD to Analog GND, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0 to 8.0V VEE to Analog GND, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.8 to -8.0V Clock Frequency, fClk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 to 400kHz Zero Offset Correction Capacitor, Co . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 20%F Electrical Characteristics: (CI = 0.1F mylar, RI = 470k @ Vref = 2V, RI = 27k @ Vref = 200mV, RC = 300k, TA = +25C ; all voltages referenced to Analog GND, Pin1, unless otherwise specified) Parameter Linearity-Output Reading Symbol VDD = 5V, VEE = -5V, Note 2 Test Conditions Vref = 2.000V Vref = 200.0mV Min -0.05 - Count - - - - - Typ 0.05 0.05 - - 0 20 Max +0.05 + Count - 3 4 0 100 Unit %rdg %rdg LSD LSD LSD pA Stability - Output Reading Symmetry - Output Reading Zero-Output Reading Bias Current Analog Input Reference Input Analog GND Common Mode Rejection Input Voltage (Pin9, Pin10) "0" Level VDD = 5V, VEE = -5V, VX = 199mV, Vref = 200mV VDD = 5V, VEE = -5V, Vref = 2000mV, Note 3 VDD = 5V, VEE = -5V, VX = 0V, Vref = 2V VDD = 5V, VEE = -5V - - VDD = 5V, VEE = -5V, fClk = 32kHz, VX = 1.4V, Vref = 2V VIL VDD = 5V, VO = 4.5V or 0.5V, Note 3 20 20 65 100 500 - pA pA dB - - 2.25 1.5 V VDD = 10V, VO = 9V or 1V, Note 3 VDD = 15V, VO = 13.5V or 1.5V, Note 3 "1" Level VIH VDD = 5V, VO = 0.5V or 4.5V, Note 3 VDD = 10V, VO = 1V or 9V, Note 3 VDD = 15V, VO = 1.5V or 13.5V, Note 3 Output Voltage (Pin14 to Pin23) "0" Level "1" Level Output Current (Pin14 to Pin23) Source Sink Input Current (DU, Pin9) Quiescent Current DC Supply Rejection VOL VSS = 0V VDD = 5V, VEE = -5V - - 3.5 7.0 11.0 - 4.50 6.75 2.75 5.50 8.25 0 3.0 4.0 - - - 0.05 V V V V V V VSS = -5V VOH VSS = 0V VSS = -5V IOH VDD = 5V, VEE = -5V VSS = 0V, VOH = 4.6V - 4.95 4.95 -0.2 -5.0 -5.0 5.0 -0.36 -4.95 - - - V V V mA VSS = -5V, VOH = 4.5V VSS = 0V, VOL = 0.4V VSS = -5V, VOL = -4.5V -0.5 0.51 1.3 - - - - -0.9 0.88 2.25 0.00001 0.9 1.8 0.5 - - - 0.3 2.0 4.0 - mA mA mA A mA mA mV/V IOL IDU IQ VDD = 5V, VEE = -5V VDD to VEE, VDD = 5V, VEE = -5V ISS = 0 VDD = 8V, VEE = -8V VDD = 5V, VEE = -5V, VDD to VEE, ISS = 0, Vref = 2V Note 2. Accuracy - The accuracy of the meter at full scale is the accuracy of the setting of the reference voltage. Zero is recalculated during each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other than positive full scale and zero is defined as the linearity specification. Note 3. Symmetry - Defined as the difference between a negative and positive reading of the same voltage at or near full scale. Note 4. Referenced to VSS for Pin9. Referenced to VEE for Pin10. Truth Table (DS1 =1) Coded Condition of MSD +0 -0 +0 UR -0 UR +1 -1 +1 OR -1 OR Q3 1 1 1 1 0 0 0 0 Q2 1 0 1 0 1 0 1 0 Q1 1 1 1 1 0 0 1 1 Q0 0 0 1 1 0 0 1 1 BCD to 7 Segment Decoding Blank Blank Blank Blank 41 01 71 31 Hook up only seg b and c to MSD Notes for Truth Table: Q3 - 1/2 digit, low for "1", high for "0" Q2 - Polarity: "1" = positive, "0" = negative Q0 - Out of range condition exists if Q0 =1. When used in conjunction with Q3 the type of out of range condition is indicated, i.e., Q3 = 0 OR or Q3 = 1 UR. When only segment b and c of the decoder are connected to the 1/2 digit of the display 4, 0, 7, and 3 appear as 1. The overrange indication (Q3 = 0 and Q0 = 1) occurs when the count is greater than 1999, e.g., 1.999V for a reference of 2V. The underrage indication, useful for autoranging circuits, occurs when the count is less than 180, e.g., o.180V for a reference of 2V. Caution: If the most significant digit is connected to a display other than a "1" only; such as a full digit display, segments other than b and c must be disconnected. The BCD ti seven decoder must blank on BCD inputs 1010 to 1111. Pin Connection Diagram VAG 1 Vref 2 VX 3 RI 4 RI/CI 5 CI 6 CO 1 7 CO 2 8 DU 9 24 VDD 23 Q3 22 Q2 21 Q1 20 Q0 19 DS 1 18 DS 2 17 DS 3 16 DS 4 15 OR 14 EOC 13 VSS CLK 1 10 CLK 2 11 VEE 12 24 13 1 12 1.300 (33.02) Max .225 (5.73) Max .520 (13.2) .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24) |
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